1. Field of the Invention
The present invention relates to a data processing apparatus, a method therefor, and a computer program that are applicable to cooperative verification of hardware (HW) and software (SW) (“Co-Verification” or “Co-Simulation”) mounted on a semiconductor device.
2. Description of the Related Art
There is proposed a method of cooperatively verifying (Co-Verification), using a host CPU (host processing apparatus: “Co-Verification System” or “Co-Simulation System”), hardware and software of a semiconductor device mounted with one target CPU and one operating system (OS) (see, for example, JP-A-2004-234528).
This method includes first to fifth steps explained below.
In the first step, the host CPU inputs and compiles a Timed software component described in a C-base language (for example, System C) as a verification model (a software model) and links the compiled Timed software component and a compiled hardware component.
In the second step, the host CPU inputs and compiles a test bench.
In the third step, the host CPU links the verification model processed in the first step and the test bench processed in the second step and generates an execution program.
In the fourth step, the host CPU executes simulation on the basis of the execution program generated in the third step.
In the fifth step, the host CPU outputs a result of the simulation in the fourth step.
As the first step, two kinds of processing explained below can be adopted.
First processing is processing as the first step for inputting a Timed software component of a binary code for host CPU as a verification model, inputting and compiling a hardware component described in a C-base language as a verification model, and linking the input Timed software component and the compiled hardware component.
Second processing is processing as the first step for inputting and compiling a Timed software component described in the C-base language as a verification model, inputting a Timed software component of a binary code for host CPU as a verification model, inputting and compiling a hardware component described in the C-base language as a verification model, and linking the compiled or input Timed software component and the compiled hardware component.
In the method disclosed in JP-A-2004-234528, when Timed software (a source code for simulation) is generated from Un-Timed software (original source code), a Basic Block is recognized with reference to an ANSI-C based source code or a binary code for host CPU.
For example, the original source code is illustrated as the Un-Timed software and the source code for simulation is illustrated as the Timed software.